One of the major trends in the semiconductor packaging industry is to use surface-mount technology (SMT) as a replacement for conventional plated-through-hole (PTH) technology. SMT offers several distinct advantages over PTH technology, such as greater packaging density, higher lead counts with shorter interconnection lengths and easier automation. Since SMT requires electronic devices and components to be mountable on the surface of a printing wiring board, the materials and structure of traditional leaded components including capacitors, resistors and inductors have to be redesigned to meet the modern-day demand for short, thin, light and small electronic devices.
Examples of semiconductor devices accomplishing these objects include “quad flat non-leaded (QFN)” packages. Quad flat non-leaded electronic devices have a relatively new package structure, in which space-consuming outer leads protruding laterally out of a package are eliminated. Instead, external electrode pads to be electrically connected to a motherboard are provided on the backside of the QFN package.
A quad flat non-leaded package, especially a leadless leadframe package (LLP) makes use of a metal leadframe-type substrate structure in the formation of a chip scale package (CSP). In a typical leadless leadframe package, a copper leadframe strip or panel is patterned by stamping or etching to define a plurality of arrays of chip substrate features. Each chip substrate feature includes a die attach pad and a plurality of contacts (bonds) disposed about their associated die attach pad. During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple each die to their associated bond pad contacts on the leadframe strip. After the wire bonding process, a synthetic resin cap is moulded over the top surface of each array of wire-bonded dice. The dice are then singulated and tested using conventional sawing and testing techniques.
In the following, referring to FIG. 5, a conventional dual row package 500 having equal spacing will be shortly explained. The conventional dual row package 500 comprises a first row 501 of terminals and a second row of terminals 502. Each of the rows comprises a plurality of terminals, which are schematically depicted as rectangular terminals 503, 504 and 505 for the first row 501 and as rectangular terminals 506 and 507 of the second row 502. Furthermore, a first arrow 508 shows a longitudinal axis of the dual row package 500 and a perpendicular direction showing towards a center of the dual row package 500 is shown by a second arrow 509. Thus, the second row 502 may form an inner row of the package. Such a conventional dual row package 500 has a spacing between the terminals of one row, i.e. in the first direction 508, the so-called pad-pitch of about 200 μm, for example. By the same time the spacing between the two rows, i.e. in the second direction 509, the so-called row-pitch is also about 200 μm. That is, the pad-pitch and the row-pitch is the same in the conventional dual row package 500.
The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques. Solder is printed well in a rectangular shape, suitably using stencil soldering. However, under reflow (heat) conditions the solder adheres to a ball and may generate shorts between adjacent pads. Thus, in order to reduce the probability of shorts, large distances between the terminals are used to be able to solder the components without opens and without shorts. However, to provide a given (desired) number of pads, larger distance between pads will result in a relatively large amount of space needed for the total package, which is a drawback in use for nowadays and future short, thin, light and small electronic devices.